State Justiication Using Genetic Algorithms in Sequential Circuit Test Generation

Complex VLSI circuits impose constraints on a test generator which are very diicult to handle using deterministic algorithms. Thus, a major goal in developing a new test generator is to have the capability of handling constraints, but without sacriicing the performance and eeectiveness of deterministic approaches. In this paper, we describe a hybrid sequential circuit test generator which combines deterministic algorithms for fault excitation and propagation with genetic algorithms for state justiication. The hybrid test generator restricts state justiication for complex circuits to the genetic approach, which is better able to handle constraints. High fault coverages were obtained for the ISCAS89 sequential benchmark circuits and several synthesized circuits, and in many cases the results are better than those for purely deterministic approaches. Results were further augmented by preceding the hybrid test generation by a fast run of simulation-based test generation controlled by a genetic algorithm.